Integrated Circuit Layout Designer Job Description Sample
Technician Senior Specialist - Integrated Circuit Layout Technician - Cadence Design Systems IC Design
Integrated Circuit Layout Technician. SBF is seeking an experienced integrated circuit technician to help advance the state of the art in infrared and visible imager readout integrated circuits (ROICs). Significant experience with physical layout of mixed signal VLSI CMOS transistor level designs is required.
The selected candidate will perform silicon layout of analog and digital submicron transistor level designs in support of advanced infrared cameras and imagers. Designs include ultralow noise analog circuit blocks, low power analog to digital conversion, high speed multi GHz data transmission and serializers. Basic Qualifications Training and experience in integrated circuit design.
Familiarity with Cadence Design Systems IC design schematic capture and layout tools. Ability to obtain a secret security clearance - must be a US Citizen. Desired skills Experience in custom CMOS integrated circuit transistor and standard cell layout, use of IC design tools – Cadence schematic and layout editor, Mentor Calibre verification.
RF and BiCMOS layout experience is a plus. As a leading technology innovation company, Lockheed Martin’s team of 113,000 people works with partners around the world to bring proven performance to our customers’ toughest challenges. Lockheed Martin has employees based in all 50 states and more than 570 facilities that span 70 countries. Join us at Lockheed Martin, where we’re engineering a better tomorrow.
*Lockheed Martin is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.
- Job Location(s): Goleta California
Power Electronics / Power Supply Engineer - Circuit & Layout Designer
Mature electrical engineering consulting firm seeking part-time or full-time experienced (5 years experience minimum (with consistent focus on power supply design, troubleshooting & testing); 10 to 20 years experience preferred) power electronics / switching power supply designer to become part of an engineering team regarding the design, upgrade and redesign of power supplies used in energy-efficient technologies including end-use products for the commercial and industrial customer sectors. This opportunity is guaranteed to provide the most interesting and rewarding power electronics experience in the industry. Preferred candidate should have experience with PSpice (or equivalent software) and other software used to design, simulate and troubleshoot power supplies; experience in working in a laboratory environment required. Experience in designing PCBs (layouts) is a plus. Experience with power factor correction (PFC) controllers and other power supply controllers (e.g., half-bridge, full-bridge) is required. Experience with test and measurement instrumentation is also required. Experience with IEEE and IEC standards regarding power supply performance is also a plus. Bachelor of Science in Electrical Engineering from an accredited university required. Master of Science in Electrical Engineering with Power Electronics emphasis is a plus.
Low-Power RF Integrated Circuit Designer (Full-Time)
Ideal candidate will design RF circuit blocks to specification, deliver design documentation and simulation results justifying design decisions.
Design entails these actions, and producing documentation of their results:
- solution space exploration: research, or based on experience
- evaluating possible candidates - judging best based on specifications
- full (PVT) verfication by simulation in Cadence environment, instructions to layout
- post-layout verification in Cadence environment
- 5+ years of experience in RF/analog integrated circuit design with Cadence tools
- Experience designing low power RF blocks such as LNA, mixer, amplifier, peak detector, imperfection compensation, and supporting circuits in the ISM bands
- MS (at least partial) level or higher in EE or related field with focus on RF/analog integrated circuit design
- Experience designing in CMOS 65nm, 55nm
- Knows how to give direction to layout engineer to help with floorplan, contingency plan for metal-mask revisions, and communicate guidelines for critical aspects of RF/analog layout
Fresh startup working at a fast pace to deliver a complex wireless system-on-a-chip that will revolutionize the VR/AR hardware space.
Team of RF/analog/mixed-signal integrated circuit designers is 1-5. Overall team size is 5-10. Individual contributions are very visible and will directly drive design success.
Easy going, focused work style. Seeking self-motivated independent designer who can effectively communicate technical and non-technical ideas succinctly. Belief that teams are more than the sum of their parts is a must.
Integrated Circuit Virtuoso Layout Engineer 3
Integrated Circuit Virtuoso Layout Engineer 3
Requisition ID: 18002910
Location(s): United States-Maryland-Linthicum
US Citizenship Required for this Position: Yes
Relocation Assistance: Relocation assistance may be available
Travel: Yes, 10 % of the Time Northrop Grumman, Mission Systems is seeking a candidate for the position of Integrated Circuit Virtuoso Layout Engineer 3 in the Electrical Design Technology (EDT) organization. The position is located at the Advanced Technology Lab (ATL) in Linthicum, MD where we design, manufacture, and test semiconductor products for internal and commercial production as well as emerging programs. The ideal candidate will have solid layout skills in Cadence Virtuoso and strong experience scripting repetitive needs in SKILL, PERL, Ocean, Linux Shell, etc. The development nature of our foundry activities will provide a willing candidate the opportunity to develop into an integral member of the foundry organization. Responsibilities include:
Generate Virtuoso layouts for Process Control Monitor (PCM) structures with guidance from process development engineers
Generate Virtuoso layouts for alignment marks with guidance from photo lithography engineers
Generate Virtuoso layouts for physical measurement structures with guidance from process development and photo lithography engineers
Generate Virtuoso schematics and layouts for test circuits that are sub-circuits of larger integrated circuits with guidance from design engineers + Participate in reticle composition and tape out support activities + Aid in troubleshooting related to all of the above + Create and document flows for future re-use and quality control MSBALTECM
This job requires a Bachelor's degree (BSEE or other Engineering discipline preferred) with 5 years of relevant experience (3 years with an MS and 0 years with a PhD). Relevant Masters level coursework or projects will be considered in lieu of relevant work experience.
Experience using Cadence tools to layout Integrated Circuits, perform Mask Layout, Full Custom Layout and/or draw structures used typically in a Microelectronics Foundry environment
Experience using Cadence Schematic Editor tools to create circuits + Demonstrated ability to script capabilities within the Cadence environment using one of several compatible scripting languages
Knowledge of Cadence XL/GXL capabilities that enhance layout task efficiency + Solid knowledge of the Cadence environment AND DRC/LVS/PEX within Cadence DIVA, Assura, PVS or Mentor Graphics Calibre + Solid interpersonal and team skills for cross-functional collaboration. High attention to detail and ability to self-check work outputs
Knowledge of semiconductor device physics, process development, analog/mixed signal integrated circuit design, manufacturing and testing
Experience taking lab measurements on process control monitor (PCM) test structures or interpreting results from automated testing of those structures
Experience utilizing the spectre simulator to verify models match measurements
Experience laying out digital standard cells and memory elements or characterizing standard cells and memories
Experience with Process Design Kit (PDK) Development (techfiles, verification rulefiles, p-cells) + Proficiency with Cadence Assura DRC/LVS/PEX or the Mentor Graphics Calibre suite of verification tools Northrop Grumman is committed to hiring and retaining a diverse workforce. We are proud to be an Equal Opportunity/Affirmative Action Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO/AA and Pay Transparency statement, please visit www.northropgrumman.com/EEO . U.S. Citizenship is required for most positions.
Title:Integrated Circuit Virtuoso Layout Engineer 3
Digital Integrated Circuit Designer
The group's quantum information science activities include the development of superconducting and trapped-ion qubits and quantum sensing with nitrogen-vacancy (NV) centers in diamond. In addition, the group has robust capabilities in classical superconducting circuits, complementary metal-oxide semiconductor (CMOS) design and fabrication, and integrated photonics. These component technologies are used in synergy with quantum information science demonstrations, as well as in standalone applications that include beyond-CMOS circuit technologies, energy-starved sensors, compact optical communication and laser radar transceivers, and microwave photonic signal processing.
Group 89, Quantum Information Sciences and Integrated Nanosystems, seeks a Digital Circuit Designer with a broad background to contribute expertise in digital and mixed-signal IC and FPGA-based designs targeting both commercial and internal process technologies and devices. This position will emphasize algorithmic and functional design, front-end modeling and verification tasks in the context of a small team where flexibility in branching beyond primary responsibilities is highly valued.
· MS degree in Computer Engineering, Electrical Engineering, Computer Science, or a related field and 2+ years’ experience.
In lieu of a MS, candidates with a BS degree and 5+ years of experience will be considered. · The ideal candidate will have a strong background in the following aspects of digital IC design: o Modeling at the register transfer level (RTL) in Verilog or VHDL (Verilog preferred) o Design of testbenches for functional verification o Synthesis using industry-standard EDA tools (RTL Compiler or Design Compiler) o Functional verification at the gate level with SDF back-annotated timing o Experience with at least one scripting language applied to IC design (shell scripting, Perl, Tcl, or Python) o Experience with FPGA-based design using Vivado, Quartus and/or Synplicity. · Experience in the following design tasks is a bonus: o Automatic place and route (Encounter preferred) o Static timing analysis o Formal verification o Physical verification – LVS and DRC (Calibre preferred) MIT Lincoln Laboratory is an Equal Employment Opportunity (EEO) employer. All qualified applicants will receive consideration for employment and will not be discriminated against on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, age, veteran status, disability status, or genetic information; U.S. citizenship is required.
Vlsi Designer - Layout And Circuit Design Multiple Openings
VLSI Layout Designer (Multiple Openings) DUTIES: Design circuit layout per specified requirements, using industry standard Electronic Design Automation (EDA) tools and technologies.
The ideal candidate will have strong Analog Layout design skills and is capable of solving device matching, Electromigration, power distribution, and circuit area restrictions, using state of the art deep sub-micron technologies. REQUIREMENTS: 10 years of experience with Certificate or 20 years of experience Strong Analog circuit layout skills Extensive experience with Cadence EDA (Composer / Virtuoso) Experience with Cadence ASSURA and Mentor CALIBRE LVS/DRC Strong oral/written communication skills; a positive, open-minded attitude; as well as an ability
Electrical Engineer Wtih Circuit Design PCB Layout
Electrical Engineer / PCB Designer Applied Dynamics International (ADI), headquartered in Ann Arbor, Michigan, is a leading supplier of model based systems engineering software, systems, and technical expertise for development and lab testing of complex control and system integration applications. Our engineers work with customers on some of the most cutting-edge technology being developed in the Aerospace and Defense community.
ADI's flagship software product, the ADvantage Framework, is a software platform providing an agile, feature-rich environment for supporting system life cycle through development, integration and test. ADI’s customers include Boeing, BAE Systems, NASA, Honeywell, Raytheon, Gulfstream, Rolls Royce, and many
Engineering Fellow Mixed Signal RF Digital Integrated Circuit Design
Job Description: The Subsystem Center in the Engineering Electrical Subsystems Directorate (ESD) is seeking to fill a mixed-signal RF/digital integrated circuit designer technical expert Fellow position.
The Fellow is responsible for architecture design of advanced Radio Frequency (RF) Application Specific Integrated Circuits (ASICs). RF ASIC applications include radar, communication links, electronic warfare, and directed energy components and systems. The Fellow should also have substantial experience in designing advanced integrated RF components including power amplifiers, low-noise amplifiers, mixers, switches, phase shifters, detectors, etc., on Silicon Germanium (SiGE) and Complementary Metal-Oxide Semiconductor (CMOS) semiconductor processes. RF frequencies of interest range from less than 1GHz to greater than 100GHz.
The Fellow should also have experience in designing digital control/interface circuitry on the same SiGE and/or CMOS processes. The Fellow should have knowledge and experience in the packaging and testing of RF ASICs. Key responsibilities include, but are not limited to, the following:
Develops RF ASIC requirements for new and emerging RF systems as well as ASIC replacements for existing RF circuit designs. Develops RF ASIC circuit designs for new and emerging RF systems as well as ASIC replacements for existing RF circuit designs. Develops test requirements and procedures for new RF ASIC designs.
Conceptual development of new configuration and applications of RF ASICs. Assists in the development of RF system requirements Development and writing of proposals. Trains and mentors less-experienced RF ASIC design engineers.
Provides technical conscience, challenged with making sure the product and process meet appropriate standards. Ensures balance with risk conditions and constraints while advising leadership Visible and accountable for technical decisions. Primary technical contact with the customer inclusive of requirements, technical commitments, IRAD, future technical needs, etc.
Lead IRAD road mapping with RMS including capital strategy. Participate in major review boards such as Engineering Review Board, Failure Review Board, Risk and Opportunity Review Board etc. Communicates and collaborates with Program Management, Product Line Chief Engineer, Functional Management, Operations and Customers.
Technically successful bringing a balanced solution within the boundary conditions set by a business solution with Program Manager. The Fellow will engage the Chief Engineer’s Office and the Product Line Chief Engineers. Required Skills, Experience & Education:
Bachelor’s degree in Electrical Engineering, or other technical related field A minimum of 12 years’ experience in RF integrated circuit design Detailed knowledge of multiple RF ASIC layout tools such as Cadence and Advanced Design System (ADS) Responsible for providing guidance, coaching / mentoring and training to other employees across the business within area of expertise. Desired Skills, Experience & Education: Master’s degree or PhD preferred in Electrical Engineering Currently hold a DoD issued security clearance of Secret or higher (a current investigation is defined as an investigation not older than six years) Nationally known as an expert in the field of RF ASIC design Participant in nationally recognized boards and committees Published papers, and submitted relevant patents Detailed knowledge electromagnetic analysis tools such as High Frequency Structure Simulator (HFSS) and/or Microwave Office Familiarity with GlobalFoundries and Tower Jazz semiconductor processes is desired Design experience in III-V semiconductor processes (e.g.
Gallium Arsenide, Gallium Nitride, Indium Phosphide) is a plus Prior active participation in a mentorship or coaching program involving several junior or mid-level engineers Security Clearance Requirements This position requires the successful issuance, transfer or maintenance of a Secret security Clearance. Non-US citizens may not be eligible to obtain a security clearance. The Defense Industrial Security Clearance Office (DISCO), an agency of the Department of Defense, handles and adjudicates the security clearance process.
Security clearance factors include, but are not limited to, allegiance to the US, foreign influence, foreign preference, criminal conduct, security violations and drug involvement. Additional detail regarding security clearance factors can be obtained by accessing the DISCO website at http://www.dss.mil/psmo-i/indus_psmo-i_interim.html Check us out on YouTube: Raytheon Company Overview Are you ready to be remarkable with Raytheon?
Visualizing the Future with Immersive Technology SeaRAM Anti-Ship Missile Defense System Make the Shift to Proactive Threat Hunting 105318 Raytheon is an Equal Opportunity/Affirmative Action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, sex, sexual orientation, gender identity, national origin, disability, or protected Veteran status.
Analog/Mixed Signal Integrated Circuit Design Engineer
Oceanit is seeking an Analog/Mixed Signal Integrated Circuit Design Engineerto work with a team of engineers to develop new ASIC designs including infrared readout integrated circuits (ROIC) as well as other analog and radio frequency (RF) solutions. The engineer will lead both front and back end design from low level, schematic to layout, verification, foundry hand-off and testing. If you are a, high-energy self-starter, a superb collaborator and have analog/mixed signal integrated circuit design experience, this position may be the one for you!
THE VALUE YOU DELIVER:* Define ASIC specifications for new projects in conjunction with cross-functional teams.
Superb technical and engineering expertise in the development of new mixed-signal circuit concepts primarily for ROIC applications and support of implementation from specification through design, fabrication and testing.
Identification and response to critical design aspects such as speed, processing capacity, power and area.
Work with a team of multi-disciplined engineers to evaluate and simulate system architecture choices, and develop and test those concepts.
Design analog and mixed signal circuit blocks as part of a larger design effort.
Bring market and competitor knowledge to help craft technical and programmatic win strategies. Provide technical expertise, knowledge, pursuit strategy, and business opportunities.
Provide technical expertise on circuitry and other RF problems.
Research technical literature, plan, design and execute projects. This involves customer interface, planning and scheduling, identifying and purchasing of equipment and supplies. THE EXPERTISE WE’RE LOOKING FOR * MS degree in Electrical Engineering or equivalent practical experience. PhD degree in Electrical Engineering preferred.
Proven track record of electrical engineering expertise – 3-5 years of experience with custom IC design.
Experience with ROIC design and focal plane arrays preferred.
Experience in transistor-level schematic design, layout, simulation and verification using Cadence or Tanner EDA.
Experience with physical design and guiding mask designers to create high quality layout.
Experience with analog/RF design using 180nm CMOS processes or below. Laboratory characterization and chip debugging experience.
Understanding of device physics and manufacturing processes.
Experience and knowledge of one or more scripting or programming languages, such as Python, C, Matlab, VHDL.
Excellent written communication and presentation skills, with the ability to clearly and competently convey technical system design and trade information to a wide range of audiences for design reviews and proposal writing. Department: Science and Technology
Location:* Honolulu, HI (Oahu)
IC Layout Mask Designer ATX
IC Layout designer
Experience in IC layout of high performance analog including block level and chip level layout requirements. Understanding of parasitic impact on circuit performance is a plus. Capable of top level floor planning with knowledge of transistor, resistor, and capacitor matching in deep sub-micron processes.
- Ability to resolve LVS/DRC errors is critical to being successful in this position.
- FinFET experience required.
- Thorough understanding of low power and DFM layout issues a plus.
- Must be able to communicate effectively with circuit designers to understand their requirements and implement the requested layout.
- Capable of using various CAD tools: Cadence Virtuoso, VXL, Assura, PVS, Caliber etc.
- Associates degree with 2 years minimum experience as an IC Layout Designer.
- Candidate must be willing to perform all aspects of IC layout.
IC Enable is an IC design and layout services company that provides solutions to semiconductor companies. We are a growing team of professionals who are looking for talented and dedicated individuals to join our organization.
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